1. Field of the Invention
The invention relates to an integrated and programmable processor for word-wise digital signal processing, comprising:
a. a multiplier element which comprises a first input and a second input for receiving two operands for multiplication and a first output for presenting a product; PA1 b. an arithmetic and logic unit which comprises a third input and a fourth input for receiving two further operands, a second output for presenting a result operand, and first accumulator means which are connected between the second output and the third output; PA1 c. a first read-write memory for the storage of data; PA1 d. connection means for connecting a control memory for the storage of control information for the other components; PA1 e. communication means, including bus connection means, for connecting said components to one another and to the environment. PA1 said first input is connected to a separate first bus, said second input and fourth input being connected to a separate second bus of said bus connection means; PA1 said third input can be coupled to the first bus; PA1 said first accumulator means comprise a third output with a first selector for forming a selectable connection to said first and second bus; PA1 said first output comprises a second selector for forming a selectable connection to said first and second bus; PA1 said first read/write memory comprises an address input and a data input which are connected to said first and second bus, and a fourth output with a third selector in order to form a selectable connection to said first and second bus. PA1 address calculation for a data memory, including associated memory access, in order to make an operand for the bus connection means available during the next instruction cycle; PA1 a data transport via at least one bus of the bus connection means; and PA1 a data processing operation in at least either the arithmetic and logic unit or the multiplier element on an operand transported via the bus connection means during said instruction cycle in order to form a result operand during this instruction cycle which is made available for transport via the bus connection means during the next or a later instruction cycle. A given degree of parallellism can thus be achieved within one instruction cycle. PA1 address calculation for a data memory for the formation of an address for the next instruction cycle; PA1 memory access in a data memory by means of an address calculated during the directly preceding instruction cycle in order to make an operand available for the bus connection means in the next instruction cycle; PA1 a data transport via at least one bus of the bus connection means; PA1 a data processing operation in at least one of the two elements arithmetic and logic unit and multiplier element on at least one operand transported via the bus connection means during said instruction cycle or during a previous instruction cycle in order to form a result operand during the interval of the same instruction cycle pulse the next instruction cycle in order to make this operand available for transport via the bus connection means during the second next instruction cycle or during a later instruction cycle, for which purpose output registers are connected to the multiplier element, and to the first read-write memory, said output registers being transparently activatable in said first state of the cycle selector, there being provided input registers for the arithmetic and logic unit and the multiplier element which are transparently activatable in both states of the cycle selector. By the interjection of the additional registers, uncoupling takes place so that the signals on the input thereof (result of an operation) are uncoupled from the signals on the output of these registers (result of a preceding operation). Due to this uncoupling, a higher processing speed can be achieved without a faster technology being required or a higher clock pulse frequency being used. The processing speed is also increased by extension of the parallel pipelining principle as will be explained in detail hereinafter. It is a minor drawback, however, that programming is now slightly more complex because each instruction word must contain elements of operations whose further execution is controlled only by later instruction words.
2. Description of the Prior Art
A data processor of this kind is known from European Patent Application No. 0086307-A2 assigned to Texas Instruments Incorporated. The known device is an integrated microcomputer in which a program bus and a data bus are provided on the chip; the exchange of program information with the environment is also possible. Furthermore, the output of the multiplier element is directly connected to one of the inputs of the arithmetic and logic unit. It has been found that the flexibility of such a processor cannot be high because of inter alia such a very direct coupling. It has also been found that the presence of only one data bus also reduces the flexibility of the processor.